1use crate::BusOp;
2use wdc65816_emu::traits::BusInterface;
3
4const RAM_LEN: usize = 1 << 24;
5
6#[derive(Debug, Clone)]
7pub struct RecordingBus {
8    pub(super) ram: Box<[u8; RAM_LEN]>,
9    pub(super) ops: Vec<BusOp>,
10}
11
12impl RecordingBus {
13    pub fn new() -> Self {
14        Self { ram: vec![0; RAM_LEN].into_boxed_slice().try_into().unwrap(), ops: Vec::new() }
15    }
16
17    pub fn clear(&mut self) {
18        self.ops.clear();
19    }
20}
21
22impl BusInterface for RecordingBus {
23    fn read(&mut self, address: u32) -> u8 {
24        let value = self.ram[address as usize];
25        self.ops.push(BusOp::Read(address, value));
26        value
27    }
28
29    fn write(&mut self, address: u32, value: u8) {
30        self.ops.push(BusOp::Write(address, value));
31        self.ram[address as usize] = value;
32    }
33
34    fn idle(&mut self) {
35        self.ops.push(BusOp::Idle);
36    }
37
38    fn nmi(&self) -> bool {
39        false
40    }
41
42    fn acknowledge_nmi(&mut self) {}
43
44    fn irq(&self) -> bool {
45        false
46    }
47
48    fn halt(&self) -> bool {
49        false
50    }
51
52    fn reset(&self) -> bool {
53        false
54    }
55}